Takeo Maeda

According to our database, Takeo Maeda authored at least 3 papers between 1989 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1998

Variable supply-voltage scheme for low-power high-speed CMOS digital design.

Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama

IEEE J. Solid State Circuits, 1998

1989

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters.

Masataka Matsui, Hiroshi Momose, Yukihiro Urakawa, Takeo Maeda, Azuma Suzuki, Nobuaki Urakawa, Katsuhiko Sato, Jun'ichi Matsunaga, Kiyofumi Ochii

IEEE J. Solid State Circuits, October, 1989

A 32 kbyte integrated cache memory.

Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Tsukasa Shirotori, Toshinari Takayanagi, Tetsuya Iizuka, Takeo Maeda, Jinichi Matsunaga, Hiromichi Fuji, Kenji Maeguchi, Kiyoshi Kobayashi, Tomoyuki Ando, Yoshiki Hayakashi, Akio Miyoshi, Kazuyuki Sato

IEEE J. Solid State Circuits, August, 1989