Takayuki Iwai

Orcid: 0000-0003-2381-6232

According to our database1, Takayuki Iwai authored at least 5 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques.
IEEE J. Solid State Circuits, 2020

2019
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019

A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2008
An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008


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