Takayoshi Shimazawa

According to our database1, Takayoshi Shimazawa authored at least 11 papers between 1994 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.
IEEE J. Solid State Circuits, 2011

Development of low power and high performance application processor (T6G) for multimedia mobile applications.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2007
An automated runtime power-gating scheme.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling.
IEEE J. Solid State Circuits, 2006

2005
A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003
A single-chip MPEG-2 codec based on customizable media embedded processor.
IEEE J. Solid State Circuits, 2003

2002
A single-chip MPEG-2 codec based on customizable media microprocessor.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000
Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor.
Proceedings of ASP-DAC 2000, 2000


1994
A 110-MHz/1-Mb synchronous TagRAM.
IEEE J. Solid State Circuits, April, 1994


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