Takashi Takemoto
Orcid: 0000-0002-5949-2252
According to our database1,
Takashi Takemoto
authored at least 39 papers
between 2006 and 2021.
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Bibliography
2021
Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes.
Soft Comput., 2021
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions.
IEEE J. Solid State Circuits, 2021
4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems.
IEEE J. Solid State Circuits, 2020
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-µm SiGe BiCMOS Technology.
IEEE J. Solid State Circuits, 2018
Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity.
Proceedings of the Theory and Practice of Natural Computing - 7th International Conference, 2018
FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018
2016
A 50-Gb/s Optical Transmitter Based on a 25-Gb/s-Class DFB-LD and a 0.18-µm SiGe BiCMOS LD Driver.
IEICE Trans. Electron., 2016
A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technology.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
2015
A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Wide-temperature-range 103.2 (25.8 × 4)-Gb/s optical link for data-center Interconnects using a 1.3-µm lens-integrated surface-emitting laser array.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnects.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion.
IEEE J. Solid State Circuits, 2014
A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects.
IEEE J. Solid State Circuits, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
A 25-Gb/s × 4-Ch, 8 × 8 mm<sup>2</sup>, 2.8-mm thick compact optical transceiver module for on-board optical interconnect.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS.
IEEE J. Solid State Circuits, 2009
10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1<sup>st</sup>-order ΔΣ modulator.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
Int. J. Bifurc. Chaos, 2007
2006
Artif. Life Robotics, 2006
Resolution independent rendering of deformable vector objects using graphics hardware.
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2006