Takashi Sato
Orcid: 0000-0002-1577-8259Affiliations:
- Kyoto University, Department of Communication and Computer Engineering, Sakyo, Kyoto, Japan
According to our database1,
Takashi Sato
authored at least 158 papers
between 1989 and 2024.
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Bibliography
2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Fast Parameter Optimization of Delayed Feedback Reservoir with Backpropagation and Gradient Descent.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility.
ACM Trans. Embed. Comput. Syst., October, 2023
Uncertainty-Aware Haptic Shared Control With Humanoid Robots for Flexible Object Manipulation.
IEEE Robotics Autom. Lett., October, 2023
Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning.
Proceedings of the IEEE International Test Conference, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks.
IEEE Trans. Computers, 2022
CoRR, 2022
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the 19th IEEE Annual Consumer Communications & Networking Conference, 2022
2021
APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations.
IEEE Trans. Inf. Forensics Secur., 2021
IACR Cryptol. ePrint Arch., 2021
Automatic Parallelism Tuning for Module Learning with Errors Based Post-Quantum Key Exchanges on GPUs.
IACR Cryptol. ePrint Arch., 2021
Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation.
CoRR, 2021
Proceedings of the 30th USENIX Security Symposium, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the WAHC '21: Proceedings of the 9th on Workshop on Encrypted Computing & Applied Homomorphic Cryptography, 2021
Motion Robust Remote Photoplethysmography via Frequency Domain Motion Artifact Reduction.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021
Heart Rate Variability Extraction using Commodity Wi-Fi Devices via Time Domain Signal Processing.
Proceedings of the IEEE EMBS International Conference on Biomedical and Health Informatics, 2021
2020
Ed-PUF: Event-Driven Physical Unclonable Function for Camera Authentication in Reactive Monitoring System.
IEEE Trans. Inf. Forensics Secur., 2020
FedNNNN: Norm-Normalized Neural Network Aggregation for Fast and Accurate Federated Learning.
CoRR, 2020
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2020, 2020
Proceedings of the ECAI 2020 - 24th European Conference on Artificial Intelligence, 29 August-8 September 2020, Santiago de Compostela, Spain, August 29 - September 8, 2020, 2020
Clustering Approach for Solving Traveling Salesman Problems via Ising Model Based Solver.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation.
Proceedings of the 29th IEEE Asian Test Symposium, 2020
Influence of Device Parameter Variability on Current Sharing of Parallel-Connected SiC MOSFETs.
Proceedings of the 29th IEEE Asian Test Symposium, 2020
A Tuning-Free Hardware Reservoir Based on MOSFET Crossbar Array for Practical Echo State Network Implementation.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Integr., 2019
Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Heart Rate Estimation during Exercise from Photoplethysmographic Signals Using Convolutional Neural Network.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
PARHELIA: Particle Filter-Based Heart Rate Estimation From Photoplethysmographic Signals During Physical Exercise.
IEEE Trans. Biomed. Eng., 2018
Efficient Mini-Batch Training on Memristor Neural Network Integrating Gradient Calculation and Weight Update.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
MRO-PUF: Physically Unclonable Function with Enhanced Resistance against Machine Learning Attacks Utilizing Instantaneous Output of Ring Oscillator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
IEICE Trans. Inf. Syst., 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Enhancing the solution quality of hardware ising-model solver via parallel tempering.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Interpolation-Based Object Detection Using Motion Vectors for Embedded Real-Time Tracking Systems.
Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2018
Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Comparative study of path selection and objective function in replacing NBTI mitigation logic.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations.
Proceedings of the 54th Annual Design Automation Conference, 2017
Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Efficient circuit failure probability calculation along product lifetime considering device aging.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing.
J. Electron. Test., 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Physically unclonable function using RTN-induced delay fluctuation in ring oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Approximated Prediction Strategy for Reducing Power Consumption of Convolutional Neural Network Processor.
Proceedings of the 2016 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
ACM J. Emerg. Technol. Comput. Syst., 2015
An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs.
IEICE Trans. Electron., 2015
ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEICE Trans. Electron., 2014
IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination.
IEICE Trans. Inf. Syst., 2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis.
IEICE Trans. Electron., 2014
Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Variability in device degradations: Statistical observation of NBTI for 3996 transistors.
Proceedings of the 44th European Solid State Device Research Conference, 2014
2013
Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element.
IEICE Trans. Electron., 2013
A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis.
IEICE Trans. Electron., 2013
High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array.
Proceedings of the Design, Automation and Test in Europe, 2013
A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis.
Proceedings of the Design, Automation and Test in Europe, 2013
An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
2010
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEICE Trans. Electron., 2010
A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation.
IEICE Trans. Electron., 2010
A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Electron., 2010
Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Decomposition of drain-current variation into gain-factor and threshold voltage variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
2009
IEEE J. Solid State Circuits, 2009
2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress.
IEICE Trans. Electron., 2008
An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Inf. Syst., 2008
Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Decoupling capacitance allocation for timing with statistical noise model and timing analysis.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution.
Proceedings of the 45th Design Automation Conference, 2008
Determination of optimal polynomial regression function to decompose on-die systematic and random variations.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Improvement of power distribution network using correlation-based regression analysis.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage Drop.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
2003
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
2001
Accurate in situ measurement of peak noise and delay change induced by interconnect coupling.
IEEE J. Solid State Circuits, 2001
2000
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
IEEE J. Solid State Circuits, 1999
1989
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989