Takashi Ohsawa

According to our database, Takashi Ohsawa authored at least 17 papers between 1989 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched Capacitors.

Yaxin Mei, Takashi Ohsawa

IEICE Trans. Electron., September, 2023

2022

A Low-Cost Training Method of ReRAM Inference Accelerator Chips for Binarized Neural Networks to Recover Accuracy Degradation due to Statistical Variabilities.

Zian Chen, Takashi Ohsawa

IEICE Trans. Electron., August, 2022

2021

Compact Model of Magnetic Tunnel Junctions for SPICE Simulation Based on Switching Probability.

Haoyan Liu, Takashi Ohsawa

IEICE Trans. Electron., 2021

2020

Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read Scheme.

Ziyue Zhang, Takashi Ohsawa

IEICE Trans. Electron., 2020

Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm.

Yue Guan, Takashi Ohsawa

IEICE Trans. Electron., 2020

2019

User- Friendly Compact Model of Magnetic Tunnel Junctions for Circuit Simulation Based on Switching Probability.

Haoyan Liu, Takashi Ohsawa

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2018

A New Read Scheme for High-Density Emerging Memories.

Takashi Ohsawa

IEICE Trans. Electron., 2018

2013

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme.

Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

IEEE J. Solid State Circuits, June, 2013

2012

Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating.

Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh

IEICE Trans. Electron., 2012

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.

Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Proceedings of the Symposium on VLSI Circuits, 2012

High-speed simulator including accurate MTJ models for spintronics integrated circuit design.

Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy Cells.

Takashi Ohsawa, Kosuke Hatsuda, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoki Higashi

IEEE J. Solid State Circuits, 2011

2006

Design of a 128-mb SOI DRAM using the floating body cell (FBC).

Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe, Shuso Fujii, Tohru Furuyama

IEEE J. Solid State Circuits, 2006

2005

A 333MHz random cycle DRAM using the floating body cell.

Kosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2002

Memory design using a one-transistor gain cell on SOI.

Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi

IEEE J. Solid State Circuits, 2002

1989

A new CR-delay circuit technology for high-density and high-speed DRAMs.

Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama

IEEE J. Solid State Circuits, August, 1989

An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application.

Tohru Furuyama, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori

IEEE J. Solid State Circuits, April, 1989