Takashi Nishimura

According to our database1, Takashi Nishimura authored at least 12 papers between 1982 and 2015.

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Bibliography

2015
Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2008
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Power reduction techniques for Dynamically Reconfigurable Processor Arrays.
Proceedings of the FPL 2008, 2008

2007
Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2006
Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

1997
Building Cyber-Community-Learning from CyberCampus[TM] Experiment.
Proceedings of the Design of Computing Systems: Cognitive Considerations, 1997

1996

1994
Fast contour line extraction algorithm with selective thresholding according to line continuity.
Syst. Comput. Jpn., 1994

1989
A 209 K-transistor ECL gate array with RAM.
IEEE J. Solid State Circuits, October, 1989

1988
Region and Keyword Extraction Based on Color Marking for Document Entry.
Proceedings of IAPR Workshop on Computer Vision, 1988

1982
Configuration Control for Evolutional Software Products.
Proceedings of the Proceedings, 1982


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