Takashi Nakada
Orcid: 0000-0001-7512-2545
According to our database1,
Takashi Nakada
authored at least 45 papers
between 2004 and 2022.
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Bibliography
2022
IEICE Trans. Inf. Syst., 2022
2021
Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing.
Integr., 2021
IEICE Trans. Inf. Syst., 2021
2020
Construction of an Efficient Divided/Distributed Neural Network Model Using Edge Computing.
IEICE Trans. Inf. Syst., 2020
An Energy-Efficient Task Scheduling for Near Real-Time Systems on Heterogeneous Multicore Processors.
IEICE Trans. Inf. Syst., 2020
Proceedings of the Eighth International Symposium on Computing and Networking, 2020
2019
Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 2019 Seventh International Symposium on Computing and Networking, 2019
2018
Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing.
IEEE Micro, 2018
IEICE Trans. Inf. Syst., 2018
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation.
IEICE Trans. Inf. Syst., 2017
Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017
Compression and Aggregation for Optimizing Information Transmission in Distributed CNN.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017
2016
A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip.
IEICE Trans. Inf. Syst., 2016
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Normally-off power management for sensor nodes of global navigation satellite system.
Proceedings of the International SoC Design Conference, 2016
2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the IEEE International Conference on Data Science and Data Intensive Systems, 2015
2014
Inf. Media Technol., 2014
A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction.
IEICE Trans. Inf. Syst., 2014
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013
Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
2011
IEICE Trans. Inf. Syst., 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
An efficient and reliable 1.5-way processor by fusion of space and time redundancies.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011
2010
A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010
Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, 2010
2008
A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions.
IPSJ Trans. Syst. LSI Des. Methodol., 2008
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008
2007
Inf. Media Technol., 2007
An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators.
Proceedings of the Proceedings 40th Annual Simulation Symposium (ANSS-40 2007), 2007
2006
An accurate and efficient simulation-based analysis for worst case interruption delay.
Proceedings of the 2006 International Conference on Compilers, 2006
Proceedings of the Proceedings 39th Annual Simulation Symposium (ANSS-39 2006), 2006
2004
Proceedings of the 12th International Workshop on Modeling, 2004