Takashi Miyamori

According to our database, Takashi Miyamori authored at least 21 papers between 1988 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2015

18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications.

Jun Tanabe, Toru Sano, Yutaka Yamada, Tomoki Watanabe, Mayu Okumura, Manabu Nishiyama, Tadakazu Nomura, Kazushige Oma, Nobuhiro Sato, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters.

Takashi Miyamori, Hui Xu, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Jun Tanabe

IEICE Trans. Electron., 2014

An evaluation of an energy efficient many-core SoC with parallelized face detection.

Hiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, Takashi Miyamori

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Development of low power many-core SoC for multimedia applications.

Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano, Jun Tanabe

Proceedings of the Design, Automation and Test in Europe, 2013

A near-future prediction method for low power consumption on a many-core processor.

Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori, Nobu Matsumoto

Proceedings of the Design, Automation and Test in Europe, 2013

2012

A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications.

Hui Xu, Jun Tanabe, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Takashi Miyamori

Proceedings of the Symposium on VLSI Circuits, 2012

A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications.

Yasuki Tanabe, Masato Sumiyoshi, Manabu Nishiyama, Itaru Yamazaki, Shinsuke Fujii, Katsuyuki Kimura, Takuma Aoyama, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.

Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki

IEEE J. Solid State Circuits, 2011

2010

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.

Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Signal and power integrity for SoCs.

Don Draper, Fabio Campi, Ram Krishnamurthy, Takashi Miyamori, Shannon Morton, Willy Sansen, Vladimir Stojanovic, John T. Stonick

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs.

Takahisa Wada, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Takashi Miyamori, Masaki Nakagawa

IEEE Trans. Very Large Scale Integr. Syst., 2009

2008

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.

Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2005

Development of Image Recognition Processor Based on Configurable Processor.

Takashi Miyamori, Jun Tanabe, Yasuhiro Taniguchi, Kenji Furukawa, Tatsuo Kozakaya, Hiroaki Nakai, Yukimasa Miyamoto, Ken-ichi Maeda, Masataka Matsui

J. Robotics Mechatronics, 2005

2003

A single-chip MPEG-2 codec based on customizable media embedded processor.

Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Mitsuo Saito, Takashi Miyamori, Goichi Ootomo, Masataka Matsui

IEEE J. Solid State Circuits, 2003

Visconti: multi-VLIW image recognition processor based on configurable processor [obstacle detection applications].

Jun Tanahe, Yasuhiro Taniguchi, Takashi Miyamori, Yukimasa Miyamoto, Hideki Takeda, Masaya Tarui, Hiromitsu Nakayama, Nohuyulu Takeda, Kenichi Maeda, Masataka Matsui

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture.

Atsushi Mizuno, Kazuyoshi Kohno, Ryuichiro Ohyama, Takahiro Tokuyoshi, Hironori Uetani, Hans Eichel, Takashi Miyamori, Nobu Matsumoto, Masataka Matsui

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

A single-chip MPEG-2 codec based on customizable media microprocessor.

Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Takashi Miyamori, Goichi Ootomo, Masataka Matsui

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

1998

REMARC: Reconfigurable Multimedia Array Coprocessor (Abstract).

Takashi Miyamori, Kunle Olukotun

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications.

Takashi Miyamori, Kunle Olukotun

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1989

The effectiveness of TRONCHIP instructions in the TX1 system.

Hidechika Kishigami, Takashi Miyamori, Misao Miyata

Proceedings of the Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, 1989

1988

Design Considerations for 32-bit Microprocessor TX3.

Kosei Okamoto, Misao Miyata, Hidechika Kishigami, Takashi Miyamori, Tai Sato

Proceedings of the COMPCON'88, Digest of Papers, Thirty-Third IEEE Computer Society International Conference, San Francisco, California, USA, February 29, 1988