Takashi Kobayashi

According to our database, Takashi Kobayashi authored at least 9 papers between 1990 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories.

Kazuo Otsuga, Hideaki Kurata, Satoshi Noda, Yoshitaka Sasago, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi

IEICE Trans. Electron., 2007

A 126 mm² 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology.

Hideaki Kurata, Satoshi Noda, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume, Kazuki Homma, Teruhiko Ito, Yoshinori Sakamoto, Masahiro Shimizu, Yoshinori Ikeda, Osamu Tsuchiya, Kazunori Furusawa

IEICE Trans. Electron., 2007

2006

A 130-nm CMOS 95-mm² 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput.

Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Keiichi Yoshida, Yoshinori Takase, Takayuki Yoshitake, Osamu Tsuchiya, Yoshinori Ikeda, Shunichi Narumi, Michitaro Kanamitsu, Kazuto Izawa, Kazunori Furusawa

IEICE Trans. Electron., 2006

2005

Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories.

Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Kazuo Otsuga, Takayuki Kawahara

IEEE J. Solid State Circuits, 2005

1999

Single-electron memory for giga-to-tera bit storage.

Kazuo Yano, Tomoyuki Ishii, Toshiaki Sano, Toshiyuki Mine, Fumio Murai, Takashi Hashimoto, Takashi Kobayashi, Tokuo Kure, Koichi Seki

Proc. IEEE, 1999

1998

Internal voltage generator for low voltage, quarter-micrometer flash memories.

Takayuki Kawahara, Syun-ichi Saeki, Yusuke Jyouno, Naoki Miyamoto, Takashi Kobayashi, Katsutaka Kimura

IEEE J. Solid State Circuits, 1998

1996

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories.

Takayuki Kawahara, Takashi Kobayashi, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, T. Adachi, Masataka Kato, Akihiko Sato, J. Yugami, Hitoshi Kume, Katsutaka Kimura

IEEE J. Solid State Circuits, 1996

1991

Performance Model of Interference Avoidance Policy Using Stochastic Petri Nets.

Takashi Kobayashi, Kenzo Kurihara

Proceedings of the Fourth International Workshop on Petri Nets and Performance Models, 1991

1990

An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller.

Koichi Seki, Hitoshi Kume, Yuzuru Ohji, Takashi Kobayashi, Atushi Hiraiwa, Takeshi Nishida, Takeshi Wada, Kazuhiro Komori, Kazuto Izawa, Toshiaki Nishimoto, Yasuroh Kubota, Kazuyoshi Shoji

IEEE J. Solid State Circuits, October, 1990