Takashi Kambe

According to our database1, Takashi Kambe authored at least 25 papers between 1981 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2013
A new delay distribution model to take long-term degradation into account.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Application-specific arithmetic circuit design for a particle tracking application.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

A circuit synthesis algorithm for coarse grained dynamic reconfigurable circuits.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2012
An effective method to use GPU for rectangle packing.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011
C-based system LSI design of a particle tracking technology.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2009
An application specific circuits design for a LVCSR system.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
A Variable Length Vector Pipeline Architecture Design Methodology.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2006
C-based design of a real time speech recognition system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2002
Hardware Algorithm Optimization Using Bach C.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001
A C-based synthesis system, Bach, and its application (invited talk).
Proceedings of ASP-DAC 2001, 2001

2000
Thread partitioning method for hardware compiler bach.
Proceedings of ASP-DAC 2000, 2000

A cell synthesis method for salicide process.
Proceedings of ASP-DAC 2000, 2000

1999
Hardware synthesis with the Bach system.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
A layout approach to monolithic microwave IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Binding and Scheduling Algorithms for Highly Retargetable Compilation.
Proceedings of the ASP-DAC '98, 1998

1997
A method of redundant clocking detection and power reduction at RT level design.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Architecture evaluation based on the datapath structure and parallel constraint.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Hybrid floorplanning based on partial clustering and module restructuring.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

VLSI Design and System Level Verification for the Mini-Disc.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Optimal Scheduling for Conditional Recource Sharing.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A layout approach to Monolithic Microwave IC.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1993
Optimal layout recycling based on graph theoretic linear programming approach.
Proceedings of the VLSI 93, 1993

1982
A placement algorithm for polycell LSI and ITS evaluation.
Proceedings of the 19th Design Automation Conference, 1982

1981
SHARPS: A hierarchical layout system for VLSI.
Proceedings of the 18th Design Automation Conference, 1981


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