Takashi Imagawa
Orcid: 0000-0002-1131-0800
According to our database1,
Takashi Imagawa
authored at least 26 papers
between 2009 and 2024.
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Bibliography
2024
A Power Reduction Scheme by Arithmetic Format Conversion for a DSP to Estimate Qubit States Under 4K Cryogenic Environment.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024
2023
IPSJ Trans. Syst. LSI Des. Methodol., 2023
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2021
MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2018
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Development of High Performance RF Modules Used in Real-time FHD Video Communication over 8x8 MIMO-OFDM System.
Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018
Development of Real-time FHD Loss-Less Video Communication over an $8\times 8$ MIMO-OFDM System.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2018
2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the 17th International Symposium on Communications and Information Technologies, 2017
2016
Processing time reduction of tone mapping based on iterative shrinkage smoothing using parallel processing.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016
Image smoothing in the spatial domain using multigrid conjugate gradient methods based on accelerated iterative shrinkage.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2016
2015
An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs.
IEICE Trans. Electron., 2015
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Image smoothing using spatial iterative methods based on accelerated iterative shrinkage.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2015
2014
Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
2013
A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis.
IEICE Trans. Electron., 2013
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA.
Proceedings of the International Symposium on Quality Electronic Design, 2013
A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis.
Proceedings of the Design, Automation and Test in Europe, 2013
2010
Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009