Takao Marukame

According to our database, Takao Marukame authored at least 12 papers between 2007 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Dynamic Firing on Static Analog/Digital Neuron Circuits with Resistive Synapses for Time-Series Neural Network.

Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Kumiko Nomura, Koichi Mizushima, Yoshifumi Nishi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Nonlinear Operation of Static-Binary Neuron Circuits and Dynamic Memristive Devices for STDP Learning.

Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Radu Berdan, Kumiko Nomura, Yoshifumi Nishi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Live Demonstration: Low-Power Static Neural Network Circuits for Long-Term Change Detection.

Takao Marukame, Toshimitsu Kitamura, Junichi Sugino, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Yoshifumi Nishi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Live Demonstration: A prototype of Analog/Digital-mixed Neural Networks for reconfigurable learning.

Takao Marukame, Yutaka Tamura, Koji Takahashi, Toshimitsu Kitamura, Takashi Takebayashi, Yoshifumi Nishi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays.

Takao Marukame, Kumiko Nomura, Mari Matusmoto, Satoshi Takaya, Yoshifumi Nishi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation.

Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology.

Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani

CoRR, 2017

Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA.

Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network.

Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Bit-flipping LDPC under noise conditions and its application to physically unclonable functions.

Takao Marukame, Alexandre Schmid

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2011

Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET

Tetsufumi Tanamoto, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Kazutaka Ikegami, Yoshiaki Saito

CoRR, 2011

2007

Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions.

Tetsuya Uemura, Takao Marukame, Ken-ichi Matsuda, Masafumi Yamamoto

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007