Takanori Saeki
According to our database1,
Takanori Saeki
authored at least 6 papers
between 1992 and 2000.
Collaborative distances:
Collaborative distances:
Timeline
1992
1993
1994
1995
1996
1997
1998
1999
2000
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1
2
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Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2000
A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand".
IEEE J. Solid State Circuits, 2000
1999
A direct-skew-detect synchronous mirror delay for application-specific integrated circuits.
IEEE J. Solid State Circuits, 1999
1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1996
IEEE J. Solid State Circuits, 1996
1993
IEEE J. Solid State Circuits, November, 1993
1992
IEEE J. Solid State Circuits, November, 1992