Takanori Saeki

According to our database1, Takanori Saeki authored at least 6 papers between 1992 and 2000.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

1992
1993
1994
1995
1996
1997
1998
1999
2000
0
1
2
1
1
1
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2000
A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand".
IEEE J. Solid State Circuits, 2000

1999
A direct-skew-detect synchronous mirror delay for application-specific integrated circuits.
IEEE J. Solid State Circuits, 1999

1998
The direct skew detect synchronous mirror delay (Direct SMD) for ASICs.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1996
A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay.
IEEE J. Solid State Circuits, 1996

1993
A 30-ns 256-Mb DRAM with a multidivided array structure.
IEEE J. Solid State Circuits, November, 1993

1992
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function.
IEEE J. Solid State Circuits, November, 1992


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