Takahisa Hiraide

According to our database, Takahisa Hiraide authored at least 6 papers between 1987 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate.

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo

IEICE Trans. Inf. Syst., 2008

2006

Test Data Compression of 100x for Scan-Based BIST.

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo

Proceedings of the 2006 IEEE International Test Conference, 2006

The Application of BIST-Aided Scan Test for Real Chips.

Hideaki Konishi, Michiaki Emori, Takahisa Hiraide

Proceedings of the 15th Asian Test Symposium, 2006

Delay defect screening for a 2.16GHz SPARC64 microprocessor.

Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2003

BIST-Aided Scan Test - A New Method for Test Cost Reduction.

Takahisa Hiraide, Kwame Osei Boateng, Hideaki Konishi, Koichi Itaya, Michiaki Emori, Hitoshi Yamanaka, Takashi Mochiyama

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

1987

Partitioning and Placement Technique for CMOS Gate Arrays.

Gotaro Odawara, Takahisa Hiraide, Osamu Nishina

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987