Takahiro Irita
According to our database1,
Takahiro Irita
authored at least 25 papers
between 1998 and 2022.
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Bibliography
2022
A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control.
IEEE J. Solid State Circuits, 2022
2021
4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2017
IEEE J. Solid State Circuits, 2017
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
2016
4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2013
Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor.
IEEE Micro, 2013
A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2010
A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits.
IEEE J. Solid State Circuits, 2010
2009
A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.
IEEE J. Solid State Circuits, 2007
In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution.
IEEE J. Solid State Circuits, 2007
A Hardware Accelerator for Java<sup>TM</sup> Platforms on a 130-nm Embedded Processor Core.
IEICE Trans. Electron., 2007
A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006
Hierarchical power distribution and power management scheme for a single chip mobile processor.
Proceedings of the 43rd Design Automation Conference, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
1999
Syst. Comput. Jpn., 1999
1998
Proceedings of the Knowledge-Based Intelligent Electronic Systems, 1998
Proceedings of the Knowledge-Based Intelligent Electronic Systems, 1998