Takahiro Hatano

According to our database1, Takahiro Hatano authored at least 10 papers between 2002 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2018
Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane.
Proceedings of the IEEE 19th International Conference on High Performance Switching and Routing, 2018

2016
Hash-table and balanced-tree based FIB architecture for CCN routers.
Proceedings of the International SoC Design Conference, 2016

2015
Lagopus FPGA - A reprogrammable data plane for high-performance software SDN switches.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2011
10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control.
Proceedings of the International SoC Design Conference, 2011

2007
Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI.
IEICE Trans. Electron., 2007

Fingerprint Verification Using Perturbation Method.
Proceedings of the IAPR Conference on Machine Vision Applications (IAPR MVA 2007), 2007

2006
Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier.
IEICE Trans. Electron., 2006

2002
Fingerprint Image Enhancement by Pixel-Parallel Processing.
Proceedings of the 16th International Conference on Pattern Recognition, 2002

A Fingerprint Verification Algorithm Using the Differential Matching Rate.
Proceedings of the 16th International Conference on Pattern Recognition, 2002

A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002


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