Takahiro Hanyu
Orcid: 0000-0002-4397-8290
According to our database1,
Takahiro Hanyu
authored at least 235 papers
between 1987 and 2024.
Collaborative distances:
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Bibliography
2024
Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network Hardware.
IEICE Trans. Inf. Syst., 2024
Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems.
IEEE Access, 2024
Design of an Energy/Area-Aware MTJ-Based Nonvolatile Register with a Reference-Load Sharing Scheme.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
Proceedings of the 54th IEEE International Symposium on Multiple-Valued Logic, 2024
Design of a High-Speed and Low-Power Threshold Adjustment Unit for Battery-Free Edge Devices.
Proceedings of the International Joint Conference on Neural Networks, 2024
2023
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing.
IEEE Trans. Neural Networks Learn. Syst., December, 2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing.
CoRR, 2023
Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems.
CoRR, 2023
Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic.
IEEE Access, 2023
Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the International Conference on Field Programmable Technology, 2023
2022
Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN.
FLAP, 2022
Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices.
IEEE Open J. Circuits Syst., 2021
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition.
IEEE J. Solid State Circuits, 2021
IEICE Trans. Inf. Syst., 2021
Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once- Write Shifting.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic.
FLAP, 2020
FLAP, 2020
FLAP, 2020
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic.
IEEE Access, 2020
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices.
Microelectron. J., 2019
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
IEEE J. Solid State Circuits, 2019
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception.
J. Signal Process. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
MTJ-based asynchronous circuits for Re-initialization free computing against power failures.
Microelectron. J., 2018
Microelectron. J., 2018
An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors.
IEEE Trans. Emerg. Top. Comput., 2017
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme.
IEICE Trans. Inf. Syst., 2017
High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation.
IEICE Trans. Inf. Syst., 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017
Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Proc. IEEE, 2016
J. Multiple Valued Log. Soft Comput., 2016
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
A study of a top-down error correction technique using Recurrent-Neural-Network-based learning.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
2015
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.
IEEE J. Solid State Circuits, 2015
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor.
Proceedings of the IECON 2015, 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model.
J. Signal Process. Syst., 2014
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Computers, 2014
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs.
IEICE Trans. Inf. Syst., 2014
IEICE Trans. Inf. Syst., 2014
Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip.
IEICE Trans. Inf. Syst., 2014
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure.
IEICE Electron. Express, 2014
Soft-error tolerant transistor/magnetic-tunnel-junction hybrid non-volatile C-element.
IEICE Electron. Express, 2014
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme.
IEICE Electron. Express, 2014
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme.
IEICE Electron. Express, 2014
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme.
IEEE J. Solid State Circuits, June, 2013
Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices.
J. Multiple Valued Log. Soft Comput., 2013
Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links.
IEICE Trans. Inf. Syst., 2013
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications.
IEICE Electron. Express, 2013
IEICE Electron. Express, 2013
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
2012
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique.
J. Multiple Valued Log. Soft Comput., 2012
Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.
Proceedings of the Symposium on VLSI Circuits, 2012
A 3.14 um<sup>2</sup> 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012
Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
High-speed simulator including accurate MTJ models for spintronics integrated circuit design.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device.
IEICE Trans. Electron., 2011
Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme.
IEICE Trans. Inf. Syst., 2010
Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link.
IEICE Trans. Inf. Syst., 2010
Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit.
IEICE Trans. Electron., 2010
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits.
IEICE Trans. Electron., 2010
Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving.
IEICE Trans. Electron., 2009
Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control.
Proceedings of the ISMVL 2009, 2009
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System.
Proceedings of the ISMVL 2009, 2009
High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling.
IEICE Trans. Electron., 2008
Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation.
IEICE Trans. Electron., 2008
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
2007
Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry.
IEICE Trans. Electron., 2007
Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing.
IEICE Trans. Electron., 2006
Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic.
IEICE Trans. Electron., 2006
IEICE Trans. Electron., 2006
IEICE Trans. Electron., 2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
2005
Control Signal Multiplexing Based Asynchronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits.
J. Multiple Valued Log. Soft Comput., 2005
Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic.
J. Multiple Valued Log. Soft Comput., 2005
Multiple-Valued Logic as a New Computing Paradigm - A Brief Survey of Higuchi's Researchon Multiple-Valued Logic.
J. Multiple Valued Log. Soft Comput., 2005
Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic.
J. Multiple Valued Log. Soft Comput., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
2004
IEEE J. Solid State Circuits, 2004
Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
2003
J. Multiple Valued Log. Soft Comput., 2003
Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimization.
J. Multiple Valued Log. Soft Comput., 2003
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
2002
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002
2001
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001
2000
Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.
Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 2000
Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
1999
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs.
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic.
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
1998
Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application.
Syst. Comput. Jpn., 1998
Design and evaluation of a digit-parallel multiple-valued content-addressable memory.
Syst. Comput. Jpn., 1998
Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
1997
One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Low-power multiple-valued current-mode integrated circuit with current-source control and its application.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
IEEE J. Solid State Circuits, 1996
IEEE J. Solid State Circuits, 1996
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996
1995
A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic.
IEEE J. Solid State Circuits, November, 1995
IEICE Trans. Inf. Syst., 1995
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995
1994
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
1993
A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions.
Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993
1992
Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
1991
A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems.
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991
1990
Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices.
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990
1989
High-density quaternary logic array chip for knowledge information processing systems.
IEEE J. Solid State Circuits, August, 1989
1987
Syst. Comput. Jpn., 1987