Takahiko Hara

According to our database1, Takahiko Hara authored at least 12 papers between 1989 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013

2012
A 151-mm<sup>2</sup> 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology.
IEEE J. Solid State Circuits, 2012

2011

2009

2006
A 146-mm<sup>2</sup> 8-gb multi-level NAND flash memory with 70-nm CMOS technology.
IEEE J. Solid State Circuits, 2006

1997
Flexible test mode approach for 256-Mb DRAM.
IEEE J. Solid State Circuits, 1997

1993
Low-power on-chip supply voltage conversion scheme for ultrahigh-density DRAMs.
IEEE J. Solid State Circuits, April, 1993

BiCMOS circuit technology for high-speed DRAMs.
IEEE J. Solid State Circuits, January, 1993

1991
A 17-ns 4-Mb CMOS DRAM.
IEEE J. Solid State Circuits, November, 1991

1989
A 45-ns 16-Mbit DRAM with triple-well structure.
IEEE J. Solid State Circuits, October, 1989

New nibbled-page architecture for high-density DRAMs.
IEEE J. Solid State Circuits, August, 1989

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode.
IEEE J. Solid State Circuits, June, 1989


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