Tak-Kei Lam

According to our database, Tak-Kei Lam authored at least 11 papers between 2010 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates).

Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

A universal macro block mapping scheme for arithmetic circuits.

Xing Wei, Yi Diao, Tak-Kei Lam, Yu-Liang Wu

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A coupling area reduction technique applying ODC shifting.

Yi Diao, Tak-Kei Lam, Xing Wei, Yu-Liang Wu

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire.

Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield.

Tak-Kei Lam, Xing Wei, Wen-Ben Jone, Yi Diao, Yu-Liang Wu

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2012

ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme.

Tak-Kei Lam, Wai-Chung Tang, Xiaoqing Yang, Yu-Liang Wu

ACM Trans. Design Autom. Electr. Syst., 2012

Almost every wire is removable: A modeling and solution for removing any circuit wire.

Xiaoqing Yang, Tak-Kei Lam, Wai-Chung Tang, Yu-Liang Wu

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques.

Fu-Shing Chim, Tak-Kei Lam, Yu-Liang Wu, Hongbing Fan

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

On applying erroneous clock gating conditions to further cut down power.

Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Logic synthesis for low power using clock gating and rewiring.

Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

ECR: a low complexity generalized error cancellation rewiring scheme.

Xiaoqing Yang, Tak-Kei Lam, Yu-Liang Wu

Proceedings of the 47th Design Automation Conference, 2010