TaiYu Cheng

According to our database, TaiYu Cheng authored at least 7 papers between 2019 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling.

Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization.

TaiYu Cheng, Yutaka Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

2021

Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling.

TaiYu Cheng, Masanori Hashimoto

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design.

Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization.

TaiYu Cheng, Yukata Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training.

TaiYu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu, Masanori Hashimoto

Integr., 2020

2019

Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier.

TaiYu Cheng, Jaehoon Yu, Masanori Hashimoto

Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019