Taisuke Matsumoto

According to our database, Taisuke Matsumoto authored at least 3 papers between 2004 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2: 1 Multiplexer and 1: 2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors.

Yutaka Arayashiki, Takashi Kamizono, Yukio Ohkubo, Taisuke Matsumoto, Yoshiaki Amano, Yutaka Matsuoka

IEICE Trans. Electron., 2013

2010

A 120-Gbit/s 1.27-W 520-mVpp 2: 1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation.

Yutaka Arayashiki, Yukio Ohkubo, Taisuke Matsumoto, Yoshiaki Amano, Akio Takagi, Yutaka Matsuoka

IEICE Trans. Electron., 2010

2004

Router selection for moving networks.

Masayuki Kumazawa, Taisuke Matsumoto, Shinkichi Ikeda, Makoto Funabiki, Hirokazu Kobayashi, Toyoki Kawahara

Proceedings of the 1st IEEE Consumer Communications and Networking Conference, 2004