Taisik Shin

According to our database, Taisik Shin authored at least 2 papers between 2014 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

A 1-Tb, 4b/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8Gb/mm2 Density.

Wanik Cho, Jongseok Jung, Jongwoo Kim, Junghoon Nam, Sangkyu Lee, Yujong Noh, Dauni Kim, Wanseob Lee, Kayoung Cho, Kwanho Kim, Heejoo Lee, Sooyeol Chai, Eunwoo Jo, Hanna Cho, Jong-Seok Kim, Chankeun Kwon, Cheolioona Park, Hveonsu Nam, Haeun Won, Taeho Kim, Kyeonghwan Park, Sanghoon Oh, Jinhyun Ban, Junyoung Park, Jae-Hyeon Shin, Taisik Shin, Junseo Jang, Jiseong Mun, Jehyun Choi, Hyunseung Choi, Sung-Wook Choi, Wonsun Park, Dongkvu Yoon, Minsu Kim, Junyoun Lim, Chiwook An, Hyunyoung Shirr, Haesoon Oh, Haechan Park, Sungbo Shim, Hwang Huh, Honasok Choi, Seungpil Lee, Jaesuna Sim, Kichan Gwon, Jumsoo Kim, Woopyo Jeong, Jungdal Choi, Kyowon Jin

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2014

19.2 A 93.4mm² 64Gb MLC NAND-flash memory with 16nm CMOS technology.

Sungdae Choi, Duckju Kim, Sungwook Choi, Byungryul Kim, Sunghyun Jung, Kichang Chun, Namkyeong Kim, Wanseob Lee, Taisik Shin, Hyunjong Jin, Hyunchul Cho, Sunghoon Ahn, Yonghwan Hong, Ingon Yang, Byoungyoung Kim, Pil-Seon Yoo, Youngdon Jung, Jinwoo Lee, Jae-Hyeon Shin, Taeyun Kim, Kunwoo Park, Jinwoong Kim

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014