Taiki Uemura

According to our database1, Taiki Uemura authored at least 24 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Comprehensive Study of SER in FDSOI-Planar: 28 nm to 18 nm Scaling Effect and Temperature Dependence.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

Soft-Error Sensitivity in SRAM Manufactured by Bulk Gate-All-Around (GAA) Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023
Impact of Design and Process on Alpha-Induced SER in 4 nm Bulk-FinFET SRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

Machine Learning Based V-ramp VBD Predictive Model Using OCD-measured Fab Parameters for Early Detection of MOL Reliability Risk.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022
Accelerator-Based Thermal-Neutron Beam by Compact and Low-Cost Moderator for Soft-Error Evaluation in Semiconductor Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Thermal-Neutron SER Mitigation by Cobalt-Contact in 7 nm Bulk-FinFET Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
Soft-Error Susceptibility in Flip-Flop in EUV 7 nm Bulk-FinFET Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020
Investigating of SER in 28 nm FDSOI-Planar and Comparing with SER in Bulk-FinFET.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Backside Alpha-Irradiation Test in Flip-Chip Package in EUV 7 nm FinFET SRAM.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Early Diagnosis and Prediction of Wafer Quality Using Machine Learning on sub-10nm Logic Technology.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Advanced Self-heating Model and Methodology for Layout Proximity Effect in FinFET Technology.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020


Reliability on EUV Interconnect Technology for 7nm and beyond.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
SEIFF: Soft Error Immune Flip-Flop for Mitigating Single Event Upset and Single Event Transient in 10 nm FinFET.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2015
Soft error immune latch design for 20 nm bulk CMOS.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Impact of package on neutron induced single event upset in 20 nm SRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Investigation of single event upset and total ionizing dose in FeRAM for medical electronic tag.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Critical charge dependence of correlation of different neutron sources for soft error testing.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server.
IEEE J. Solid State Circuits, 2014

2013
A 10<sup>th</sup> generation 16-core SPARC64 processor for mission-critical UNIX server.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
Investigation of multi cell upset in sequential logic and validity of redundancy technique.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

2008
Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008


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