Taiji Ema

According to our database, Taiji Ema authored at least 3 papers between 1991 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic.

Harsh N. Patel, Abhishek Roy, Farah B. Yahya, Ningxi Liu, Benton H. Calhoun, Kazuyuki Kumeno, Makoto Yasuda, Akihiko Harada, Taiji Ema

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2013

Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias.

Vineet Agrawal, N. Kepler, David Kidd, Gokul Krishnan, Samuel Leshner, T. Bakishev, D. Zhao, P. Ranade, R. Roy, M. Wojko, Lawrence T. Clark, Robert Rogenmoser, M. Hori, Taiji Ema, S. Moriwaki, T. Tsuruta, T. Yamada, J. Mitani, S. Wakayama

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

1991

A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture.

Masao Taguchi, Hiroyoshi Tomita, Toshiya Uchida, Yasuhiro Ohnishi, Kimiaki Sato, Taiji Ema, Masaaki Higashitani, Takashi Yabu

IEEE J. Solid State Circuits, November, 1991