Taigon Song
Orcid: 0000-0001-5243-4132
According to our database1,
Taigon Song
authored at least 40 papers
between 2011 and 2024.
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Bibliography
2024
Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node.
IEEE Access, 2024
FS2K: A Forksheet FET Technology Library and a Study of VLSI Prediction for 2nm and Beyond.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop Reduction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
T<sup>3</sup>L: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023
IEEE Trans. Very Large Scale Integr. Syst., February, 2023
Cache Register Sharing Structure for Channel-level Near-memory Processing in NAND Flash Memory.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the 20th International SoC Design Conference, 2023
High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture.
Proceedings of the 20th International SoC Design Conference, 2023
2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Novel Processing Unit and Architecture for Process-In Memory (PIM) in NAND Flash Memory.
Proceedings of the 19th International SoC Design Conference, 2022
Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs.
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022
A Convenient Implementation of the Ternary Logic: Using Anti-Ambipolar Transistors and PMOS Based on Printed Carbon Nanotubes.
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
2021
An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs).
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm.
IEEE Access, 2020
A Prediction Scheme in Spiking Neural Network (SNN) Hardware for Ultra-low Power Consumption.
Proceedings of the International SoC Design Conference, 2020
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
2015
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).
IEEE Trans. Computers, 2015
J. Inform. and Commun. Convergence Engineering, 2015
J. Inform. and Commun. Convergence Engineering, 2015
Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 48th Design Automation Conference, 2011