Tai-Chen Chen

According to our database¹, Tai-Chen Chen authored at least 18 papers between 2001 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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Links

On csauthors.net:

Bibliography

2022

Flexible Multiple-Objective Reinforcement Learning for Chip Placement.

[BibT_eX]

[DOI]

CoRR, 2022

Flexible chip placement via reinforcement learning: late breaking results.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2020

Automatic Floorplanning for AI SoCs.

[BibT_eX]

[DOI]

Tai-Chen Chen

Pei-Yu Lee

Tung-Chieh Chen

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

2014

The overview of 2014 CAD contest at ICCAD.

[BibT_eX]

[DOI]

Iris Hui-Ru Jiang

Natarajan Viswanathan

Tai-Chen Chen

Jin-Fu Li

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Design-for-debug routing for FIB probing.

[BibT_eX]

[DOI]

Chia-Yi Lee

Tai-Hung Li

Tai-Chen Chen

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Electromigration- and obstacle-avoiding routing tree construction.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

LASER: layout-aware analog synthesis environment on laker.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Native-conflict-avoiding track routing for double patterning technology.

[BibT_eX]

[DOI]

Bi-Ting Lai

Tai-Hung Li

Tai-Chen Chen

Proceedings of the IEEE 25th International SOC Conference, 2012

Escape routing of differential pairs considering length matching.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Micro-bump assignment for 3D ICs using order relation.

[BibT_eX]

[DOI]

Ta-Yu Kuan

Yi-Chun Chang

Tai-Chen Chen

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

ILP-based inter-die routing for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Predictive Formulae for OPC With Applications to Lithography-Friendly Routing.

[BibT_eX]

[DOI]

Tai-Chen Chen

Guang-Wan Liao

Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2007

Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction.

[BibT_eX]

[DOI]

Tai-Chen Chen

Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

A novel framework for multilevel full-chip gridless routing.

[BibT_eX]

[DOI]

Tai-Chen Chen

Yao-Wen Chang

Shyh-Chang Lin

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Multilevel full-chip gridless routing considering optical proximity correction.

[BibT_eX]

[DOI]

Tai-Chen Chen

Yao-Wen Chang

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Timing modeling and optimization under the transmission line model.

[BibT_eX]

[DOI]

Tai-Chen Chen

Song-Ra Pan

Yao-Wen Chang

IEEE Trans. Very Large Scale Integr. Syst., 2004

2001

Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model.

[BibT_eX]

[DOI]

Tai-Chen Chen

Song-Ra Pan

Yao-Wen Chang

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Tai-Chen Chen

Timeline

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Links

On csauthors.net:

Bibliography

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