Taher Daud

According to our database1, Taher Daud authored at least 19 papers between 1990 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2008
Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008

Self-Reconfigurable Analog Array Integrated Circuit Architecture for Space Applications.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007
Adaptive and Evolvable Analog Electronics for Space Applications.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2007

Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2005
Transistor-Level Circuit Experiments Using Evolvable Hardware.
Proceedings of the Artificial Intelligence and Knowledge Engineering Applications: A Bioinspired Approach: First International Work-Conference on the Interplay Between Natural and Artificial Computation, 2005

2004
Evolutionary recovery of electronic circuits from radiation induced faults.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004

2003
Speed Enhancement with Soft Computing Hardware.
Proceedings of the Artificial Neural Networks and Neural Information Processing, 2003

2001
Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips.
IEEE Trans. Very Large Scale Integr. Syst., 2001

2000
Evolution of Analog Circuits on Field Programmable Transistor Arrays.
Proceedings of the 2nd NASA / DoD Workshop on Evolvable Hardware (EH 2000), 2000

1999
HONORS: : Advanced miniature processing hardware for ATR applications.
Neurocomputing, 1999

Cascade Error Projection: A Learning Algorithm for Hardware Implementation.
Proceedings of the Foundations and Tools for Neural Modeling, 1999

Cascade error projection with low bit weight quantization for high order correlation data.
Proceedings of the International Joint Conference Neural Networks, 1999

1996
Radiation behavior of analog neural network chips.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

Cascade error projection: a new learning algorithm.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

1995
Analog 3-D Neuroprocessor for Fast Frame Focal Plane Image Processing.
Simul., 1995

1992
Analog VLSI neural networks: implementation issues and examples in optimization and supervised learning.
IEEE Trans. Ind. Electron., 1992

Cascaded VLSI neural network chips: Hardware learning for pattern recognition and classification.
Simul., 1992

1991
Competitive neural architecture for hardware solution to the assignment problem.
Neural Networks, 1991

1990
Analog parallel processor hardware for high-speed pattern recognition.
Proceedings of the Visual Communications and Image Processing '90: Fifth in a Series, 1990


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