Taha Soliman

According to our database, Taha Soliman authored at least 21 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Accelerating Automated Driving and ADAS Using HW/SW Codesign.

Shubham Rai, Cecilia De la Parra, Martin Rapp, Jan Micha Borrmann, Nina Bretz, Stefan Metzlaff, Taha Soliman, Christoph Schorn

Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

AIO: An Abstraction for Performance Analysis Across Diverse Accelerator Architectures.

Joseph Rogers, Taha Soliman, Magnus Jahre

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

Error Detection and Correction Codes for Safe In-Memory Computations.

Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn

Proceedings of the IEEE European Test Symposium, 2024

CoNAX: Towards Comprehensive Co-Design Neural Architecture Search Using HW Abstractions.

Yannick Braatz, Taha Soliman, Shubham Rai, Dennis Sebastian Rieber, Oliver Bringmann

Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023

Demonstration of Differential Mode Ferroelectric Field-Effect Transistor Array-Based in-Memory Computing Macro for Realizing Multiprecision Mixed-Signal Artificial Intelligence Accelerator.

Vivek Parmar, Franz Müller, Jing-Hua Hsuen, Sandeep Kaur Kingra, Nellie Laleni, Yannick Raffel, Maximilian Lederer, Alptekin Vardar, Konrad Seidel, Taha Soliman, Tobias Kirchner, Tarek Ali, Stefan Dünkel, Sven Beyer, Tian-Li Wu, Sourav De, Manan Suri, Thomas Kämpfe

Adv. Intell. Syst., June, 2023

Torwards Variability Immune Scalable FeFET-based Macros for IMC DNN Accelerators.

Nellie Laleni, Taha Soliman, Cecilia De la Parra, Franz Müller, Tobias Kirchner, Andre Guntoro, Thomas Kämpfe, Norbert Wehn, T. Jang

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

SimPyler: A Compiler-Based Simulation Framework for Machine Learning Accelerators.

Yannick Braatz, Dennis Sebastian Rieber, Taha Soliman, Oliver Bringmann

Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

Simulation-driven Latency Estimations for Multi-core Machine Learning Accelerators.

Yannick Braatz, Dennis Sebastian Rieber, Taha Soliman, Oliver Bringmann

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

FELIX: A Ferroelectric FET Based Low Power Mixed-Signal In-Memory Architecture for DNN Acceleration.

Taha Soliman, Nellie Laleni, Tobias Kirchner, Franz Müller, Ashish Shrivastava, Thomas Kämpfe, Andre Guntoro, Norbert Wehn

ACM Trans. Embed. Comput. Syst., November, 2022

Ultra-low power approximate processing-in-memory acceleration for deep neural networks = Approximative Prozessierung viellagiger neuronaler Netze in Speichermatrizen für Systeme mit ultra-geringer Leistungsaufnahme.

Taha Soliman

PhD thesis, 2022

Increasing Throughput of In-Memory DNN Accelerators by Flexible Layerwise DNN Approximation.

Cecilia De la Parra, Taha Soliman, Andre Guntoro, Akash Kumar, Norbert Wehn

IEEE Micro, 2022

A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.

Chirag Sudarshan, Taha Soliman, Jan Lappas, Christian Weis, Mohammad Hassani Sadi, Matthias Jung, Andre Guntoro, Norbert Wehn

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

FeFET versus DRAM based PIM Architectures: A Comparative Study.

Chirag Sudarshan, Taha Soliman, Thomas Kämpfe, Christian Weis, Norbert Wehn

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators.

Taha Soliman, Amro Eldebiky, Cecilia De la Parra, Andre Guntoro, Norbert Wehn

Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

2021

Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design.

Cecilia De la Parra, Ahmed El-Yamany, Taha Soliman, Akash Kumar, Norbert Wehn, Andre Guntoro

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs.

Chirag Sudarshan, Taha Soliman, Cecilia De la Parra, Christian Weis, Leonardo Ecco, Matthias Jung, Norbert Wehn, Andre Guntoro

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Adaptable Approximation Based on Bit Decomposition for Deep Neural Network Accelerators.

Taha Soliman, Cecilia De la Parra, Andre Guntoro, Norbert Wehn

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks.

Taha Soliman, Ricardo Olivo, Tobias Kirchner, Maximilian Lederer, Thomas Kämpfe, Andre Guntoro, Norbert Wehn

Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Enhancing the Utilization of Dot-Product Engines in Deep Learning Accelerators.

Taha Soliman, Armin Runge, Leonardo Ecco

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

Efficient FeFET Crossbar Accelerator for Binary Neural Networks.

Taha Soliman, Ricardo Olivo, Tobias Kirchner, Cecilia De la Parra, Maximilian Lederer, Thomas Kämpfe, Andre Guntoro, Norbert Wehn

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

Fast validation of DRAM protocols with timed petri nets.

Matthias Jung, Kira Kraft, Taha Soliman, Chirag Sudarshan, Christian Weis, Norbert Wehn

Proceedings of the International Symposium on Memory Systems, 2019