Taewhan Kim
This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.
Known people with the same name:
- Taewhan Kim 001 (Seoul National University, Department of Electrical and Computer Engineering, Seoul, Korea)
- Taewhan Kim 002 (Yonsei University, Seoul, Korea)
Bibliography
2024
RAD: A Dataset and Benchmark for Real-Life Anomaly Detection with Robotic Observations.
CoRR, 2024
IFCap: Image-like Retrieval and Frequency-based Entity Filtering for Zero-shot Captioning.
Proceedings of the 2024 Conference on Empirical Methods in Natural Language Processing, 2024
2022
J. Comput. Sci. Eng., 2022
Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022
2021
Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits.
Integr., 2021
2020
PV-MAC: Multiply-and-accumulate unit structure exploiting precision variability in on-device convolutional neural networks.
Integr., 2020
Sparsity Reduction Technique Using Grouping Method for Matrix Factorization in Differentially Private Recommendation Systems.
IEICE Trans. Inf. Syst., 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
2018
Memory Access Driven Memory Layout and Block Replacement Techniques for Compressed Deep Neural Networks.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Energy-optimal dynamic voltage scaling in multicore platforms with reconfigurable power distribution network.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis.
Integr., 2014
Integr., 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the Sixth International Conference on Digital Image Processing, 2014
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Comput. J., 2012
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
An energy-optimal algorithm for temperature-aware idle time distribution considering mode transition overhead.
Proceedings of the International SoC Design Conference, 2011
Proceedings of the International SoC Design Conference, 2011
An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC.
Comput. J., 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Technique for controlling power-mode transition noise in distributed sleep transistor network.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IET Comput. Digit. Tech., 2009
Interconnect and communication synthesis for distributed register-file microarchitecture.
IET Comput. Digit. Tech., 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
ACM Trans. Embed. Comput. Syst., 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Timing variation-aware high level synthesis: Current results and research challenges.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
2005
ACM Trans. Embed. Comput. Syst., 2005
Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
J. Circuits Syst. Comput., 2003
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
An integrated algorithm for memory allocation and assignment in high-level synthesis.
Proceedings of the 39th Design Automation Conference, 2002
2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000