Taewhan Kim
Orcid: 0000-0003-2376-4970
According to our database1,
Taewhan Kim
authored at least 228 papers
between 1991 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024
Recap of the 29th Edition of the Asia and South Pacific Design Automation Conference (ASPDAC 2024).
IEEE Des. Test, June, 2024
Enhancing Design Qualities Utilizing Multibit Flip-Flops: A Design and Technology Co-Optimization Driven Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024
CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
Integr., 2024
Integr., 2024
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model.
Proceedings of the 2024 International Symposium on Physical Design, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
IEEE Trans. Very Large Scale Integr. Syst., May, 2023
Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Optimizing Timing for Multi-bit Flip-Flop Intensive Designs Compatible with Commercial EDA Flow.
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks: Signed-Digit Representation-Based Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
J. Comput. Sci. Eng., 2022
Speeding-up neuromorphic computation for neural networks: Structure optimization approach.
Integr., 2022
Comput. Educ., 2022
Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Pin Accessibility-driven Placement Optimization with Accurate and Comprehensive Prediction Model.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach.
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Allocation of Multibit Retention Flip-Flops for Power Gated Circuits: Algorithm-Design Unified Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
J. Circuits Syst. Comput., 2021
Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits.
Integr., 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Minimally Allocating Always-on State Retention Storage for Supporting Power Gating Circuits.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage.
Integr., 2020
PV-MAC: Multiply-and-accumulate unit structure exploiting precision variability in on-device convolutional neural networks.
Integr., 2020
Sparsity Reduction Technique Using Grouping Method for Matrix Factorization in Differentially Private Recommendation Systems.
IEICE Trans. Inf. Syst., 2020
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Integr., 2019
SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
2018
Memory Access Driven Memory Layout and Block Replacement Techniques for Compressed Deep Neural Networks.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Energy-optimal dynamic voltage scaling in multicore platforms with reconfigurable power distribution network.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Structure optimizations of neuromorphic computing architectures for deep neural network.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes.
Integr., 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Clock buffer polarity assignment utilizing useful clock skews for power noise reduction.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis.
Integr., 2014
Integr., 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the Sixth International Conference on Digital Image Processing, 2014
Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012
ACM Trans. Design Autom. Electr. Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Comput. J., 2012
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
ACM Trans. Design Autom. Electr. Syst., 2011
Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
An energy-optimal algorithm for temperature-aware idle time distribution considering mode transition overhead.
Proceedings of the International SoC Design Conference, 2011
Proceedings of the International SoC Design Conference, 2011
Proceedings of the International SoC Design Conference, 2011
WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing.
Proceedings of the 48th Design Automation Conference, 2011
An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Task-Level Dynamic Voltage Scaling for Embedded System Design: Recent Theoretical Results.
J. Comput. Sci. Eng., 2010
Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC.
Comput. J., 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew.
Proceedings of the International Green Computing Conference 2010, 2010
Proceedings of the 47th Design Automation Conference, 2010
Technique for controlling power-mode transition noise in distributed sleep transistor network.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
ACM Trans. Design Autom. Electr. Syst., 2009
J. Circuits Syst. Comput., 2009
IET Comput. Digit. Tech., 2009
Interconnect and communication synthesis for distributed register-file microarchitecture.
IET Comput. Digit. Tech., 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization.
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
ACM Trans. Embed. Comput. Syst., 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Timing variation-aware high level synthesis: Current results and research challenges.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
2006
J. VLSI Signal Process., 2006
J. VLSI Signal Process., 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
J. Circuits Syst. Comput., 2006
Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
2005
ACM Trans. Embed. Comput. Syst., 2005
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design.
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 42nd Design Automation Conference, 2005
2004
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Trans. Computers, 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 41th Design Automation Conference, 2004
Memory access scheduling and binding considering energy minimization in multi-bank memory systems.
Proceedings of the 41th Design Automation Conference, 2004
An integrated approach to timing-driven synthesis and placement of arithmetic circuits.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.
IEEE Trans. Very Large Scale Integr. Syst., 2003
ACM Trans. Design Autom. Electr. Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
J. Circuits Syst. Comput., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design.
Proceedings of the 40th Design Automation Conference, 2003
2002
J. VLSI Signal Process., 2002
ACM Trans. Design Autom. Electr. Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
J. Circuits Syst. Comput., 2002
J. Circuits Syst. Comput., 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
An integrated algorithm for memory allocation and assignment in high-level synthesis.
Proceedings of the 39th Design Automation Conference, 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
J. VLSI Signal Process., 2001
IEEE Trans. Computers, 2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
Proceedings of the 38th Design Automation Conference, 2001
Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders.
Proceedings of ASP-DAC 2001, 2001
2000
An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization.
VLSI Design, 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders.
J. Circuits Syst. Comput., 2000
J. Circuits Syst. Comput., 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis.
Proceedings of the 37th Conference on Design Automation, 2000
A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper).
Proceedings of ASP-DAC 2000, 2000
1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
1998
J. VLSI Signal Process., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Proceedings of the 35th Conference on Design Automation, 1998
1996
J. VLSI Signal Process., 1996
1995
Integr., 1995
1994
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
Proceedings of the European Design Automation Conference 1993, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1991
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991