Taekseung Kim

According to our database1, Taekseung Kim authored at least 5 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2018
A Quasi-Digital Ultra-Fast Capacitor-Less Low-Dropout Regulator Based on Comparator Control for x8 Current Spike of PCRAM Systems.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2015
Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Auto-Scaling Overdrive Method Using Adaptive Charge Amplification for PRAM Write Performance Enhancement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014


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