Taeko Matsunaga

According to our database, Taeko Matsunaga authored at least 8 papers between 2007 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

An Exact Approach for GPC-Based Compressor Tree Synthesis.

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2011

Multi-Operand Adder Synthesis Targeting FPGAs.

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs.

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2010

Multi-operand adder synthesis on FPGAs using generalized parallel counters.

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Framework for Parallel Prefix Adder Synthesis Considering Switching Activities.

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

IPSJ Trans. Syst. LSI Des. Methodol., 2009

2008

Synthesis of parallel prefix adders considering switching activities.

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

Proceedings of the 26th International Conference on Computer Design, 2008

2007

Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders.

Taeko Matsunaga, Yusuke Matsunaga

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Area minimization algorithm for parallel prefix adders under bitwise delay constraints.

Taeko Matsunaga, Yusuke Matsunaga

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007