Taehyeong Park

Orcid: 0000-0003-4059-597X

According to our database1, Taehyeong Park authored at least 9 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2024
Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces.
IEEE J. Solid State Circuits, October, 2024

A Fully Integrated Nine-Ratio Switched-Capacitor Converter With Overlapped-Conversion-Ratio Modulation for IoT Applications.
IEEE J. Solid State Circuits, October, 2024

A Fully Integrated Dual-Output Continuously Scalable-Conversion-Ratio SC Converter for Battery-Powered IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024

A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications.
IEEE J. Solid State Circuits, February, 2024

2023
A Thermoelectric Energy-Harvesting Interface With Dual-Conversion Reconfigurable DC-DC Converter and Instantaneous Linear Extrapolation MPPT Method.
IEEE J. Solid State Circuits, 2023

Orchestrating Large-Scale SpGEMMs using Dynamic Block Distribution and Data Transfer Minimization on Heterogeneous Systems.
Proceedings of the 39th IEEE International Conference on Data Engineering, 2023

Virtual PIM: Resource-Aware Dynamic DPU Allocation and Workload Scheduling Framework for Multi-DPU PIM Architecture.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022
A 97.9% Peak Efficiency 9 V Output Three-Switch Hybrid Buck-Boost Power Stage Using 5 V CMOS.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

2021
Federated Learning for Face Recognition.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021


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