6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier.

[BibT_eX]

[DOI]

Byoung-Joo Yoo

Dong-Hyuk Lim

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018

A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 103.125-Gb/s Reverse Gearbox IC in 40-nm CMOS for Supporting Legacy 10- and 40-GbE Links.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

2016

A Power-and-Area Efficient 10 × 10 Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2016

2015

An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2015

A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2005

Reconstruction of 3D object space from imagery by feature-based matching.

[BibT_eX]

[DOI]

Yushin Ahn

Taehun Yoon

Toni Schenk

Proceedings of the IEEE International Geoscience & Remote Sensing Symposium, 2005

Taehun Yoon

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