Taehui Na
Orcid: 0000-0001-8823-0625
According to our database1,
Taehui Na
authored at least 27 papers
between 2013 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Spin-Transfer-Torque Magnetic-Tunnel-Junction-Based Low-Power Nonvolatile Flip-Flop Designs in the Subthreshold Voltage Region.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
Ternary Output Binary Neural Network With Zero-Skipping for MRAM-Based Digital In-Memory Computing.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023
Offset-Canceling Current-Latched Sense Amplifier With Slow Rise Time Control and Reference Voltage Biasing Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
2021
Offset Voltage Analysis and Enable Signal Rise Time Control Based Offset Reduction Technique of Current-Latched Sense Amplifier.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
2020
Robust Offset-Cancellation Sensing-Circuit-Based Spin-Transfer-Torque Nonvolatile Flip-Flop.
IEEE Access, 2020
Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region.
IEEE Access, 2020
2019
Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2019
2018
Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2017
A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017
2016
An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Equalization scheme analysis for high-density spin transfer torque random access memory.
Proceedings of the International SoC Design Conference, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Reference-circuit analysis for high-bandwidth spin transfer torque random access memory.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013