Taeho Lee
Orcid: 0000-0001-5887-3371Affiliations:
- Korea Advanced Institute of Science and Technology (KAIST), Department of Electronic Engineering, Daejeon, Korea (PhD 2016)
According to our database1,
Taeho Lee
authored at least 8 papers
between 2015 and 2017.
Collaborative distances:
Collaborative distances:
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Bibliography
2017
A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network.
IEEE Trans. Very Large Scale Integr. Syst., 2017
An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator.
IEEE Trans. Very Large Scale Integr. Syst., 2016
A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method.
IEEE Trans. Very Large Scale Integr. Syst., 2016
A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
2015
An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2015
An integrated time register and arithmetic circuit with combined operation for time-domain signal processing.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015