Taehee Cho
According to our database1,
Taehee Cho
authored at least 2 papers
between 2001 and 2016.
Collaborative distances:
Collaborative distances:
Timeline
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2016
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Bibliography
2016
A 12 bit, 2-MS/s, 0.016-mm<sup>2</sup> column-parallel readout cyclic ADC, having 50% reduced slew rate requirement due to feed-forward spike eliminator.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2001
A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes.
IEEE J. Solid State Circuits, 2001