Tae Woo Oh
Orcid: 0000-0002-7545-2429Affiliations:
- Yonsei University, Seoul, South Korea
According to our database1,
Tae Woo Oh
authored at least 20 papers
between 2016 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
Design of Physically Unclonable Function Using Ferroelectric FET With Auto Write-Back Technique for Resource-Limited IoT Security.
IEEE Internet Things J., 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, 2023
2022
SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling.
IEEE J. Solid State Circuits, 2022
2021
Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation.
IEEE Access, 2021
Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells.
IEEE Access, 2021
IEEE Access, 2021
Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM.
IEEE Access, 2021
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2020
pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
2019
Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving.
IEEE J. Solid State Circuits, 2019
2018
Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Novel Heat-Aware Write Method with Optimized Heater Material and Structure in sub-20 nm PRAM for Low Energy Operation.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016