Tae Jun Ham

Orcid: 0000-0002-2669-6849

Affiliations:
  • Seoul National University, Korea


According to our database1, Tae Jun Ham authored at least 37 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2024
An LSM Tree Augmented with B<sup>+</sup> Tree on Nonvolatile Memory.
ACM Trans. Storage, 2024

2023
MaPHeA: A Framework for Lightweight Memory Hierarchy-aware Profile-guided Heap Allocation.
ACM Trans. Embed. Comput. Syst., 2023

2022
Architecting a Flash-Based Storage System for Low-Cost Inference of Extreme-Scale DNNs.
IEEE Trans. Computers, 2022

Layerweaver+: A QoS-Aware Layer-Wise DNN Scheduler for Multi-Tenant Neural Processing Units.
IEICE Trans. Inf. Syst., 2022

ULPPACK: Fast Sub-8-bit Matrix Multiply on Commodity SIMD Hardware.
Proceedings of the Fifth Conference on Machine Learning and Systems, 2022

ANNA: Specialized Architecture for Approximate Nearest Neighbor Search.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

L3: Accelerator-Friendly Lossless Image Format for High-Resolution, High-Throughput DNN Training.
Proceedings of the Computer Vision - ECCV 2022, 2022

2021
Accelerating Genomic Data Analytics With Composable Hardware Acceleration Framework.
IEEE Micro, 2021

ASAP: Fast Mobile Application Switch via Adaptive Prepaging.
Proceedings of the 2021 USENIX Annual Technical Conference, 2021

MaPHeA: a lightweight memory hierarchy-aware profile-guided heap allocation framework.
Proceedings of the LCTES '21: 22nd ACM SIGPLAN/SIGBED International Conference on Languages, 2021

ELSA: Hardware-Software Co-design for Efficient, Lightweight Self-Attention Mechanism in Neural Networks.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

BOSS: Bandwidth-Optimized Search Accelerator for Storage-Class Memory.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Layerweaver: Maximizing Resource Utilization of Neural Processing Units via Layer-Wise Scheduling.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Behemoth: A Flash-centric Training Accelerator for Extreme-scale DNNs.
Proceedings of the 19th USENIX Conference on File and Storage Technologies, 2021

FlashNeuron: SSD-Enabled Large-Batch Training of Very Deep Neural Networks.
Proceedings of the 19th USENIX Conference on File and Storage Technologies, 2021

MERCI: efficient embedding reduction on commodity hardware via sub-query memoization.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
The MosaicSim Simulator (Full Technical Report).
CoRR, 2020

Graphene: Strong yet Lightweight Row Hammer Protection.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

A Case for Hardware-Based Demand Paging.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

A Specialized Architecture for Object Serialization with Applications to Big Data Analytics.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Genesis: A Hardware Acceleration Framework for Genomic Data Analysis.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Unlocking Wordline-level Parallelism for Fast Inference on RRAM-based DNN Accelerator.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

A<sup>3</sup>: Accelerating Attention Mechanisms in Neural Networks with Approximation.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

IIU: Specialized Architecture for Inverted Index Search.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Efficient Data Supply for Parallel Heterogeneous Architectures.
ACM Trans. Archit. Code Optim., 2019

SSDStreamer: Specializing I/O Stack for Large-Scale Machine Learning.
IEEE Micro, 2019

Eager Memory Management for In-Memory Data Analytics.
IEICE Trans. Inf. Syst., 2019

Asynchronous I/O Stack: A Low-latency Kernel I/O Stack for Ultra-Low Latency SSDs.
Proceedings of the 2019 USENIX Annual Technical Conference, 2019

Practical Erase Suspension for Modern Low-latency SSDs.
Proceedings of the 2019 USENIX Annual Technical Conference, 2019

Charon: Specialized Near-Memory Processing Architecture for Clearing Dead Objects in Memory.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018
Data Access Optimization in Accelerator-Oriented Heterogeneous Architecture through Decoupling and Memory Hierarchy Specialization
PhD thesis, 2018

2017
Decoupling Data Supply from Computation for Latency-Tolerant Communication in Heterogeneous Architectures.
ACM Trans. Archit. Code Optim., 2017

2016
Graphicionado: A high-performance and energy-efficient accelerator for graph analytics.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2015
DeSC: decoupled supply-compute communication management for heterogeneous architectures.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

2013
Disintegrated control for energy-efficient and heterogeneous memory systems.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013


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