Tae-ho Shin

Orcid: 0000-0002-7932-1995

According to our database1, Tae-ho Shin authored at least 8 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

A comparison between centralized and asynchronous federated learning approaches for survival outcome prediction using clinical and PET data from non-small cell lung cancer patients.
Comput. Methods Programs Biomed., 2024

2023
LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids.
CoRR, 2022

2021
A SCAN Chain Generator for Verification of Full-Custom Integrated Circuits.
Proceedings of the 18th International SoC Design Conference, 2021

2011
Resource minimized static mapping and dynamic scheduling of SDF graphs.
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011


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