Tadayuki Taura

According to our database1, Tadayuki Taura authored at least 10 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
High-Density and Large-Scale MEA System Featuring 236, 880 Electrodes at 11.72μm Pitch for Neuronal Network Analysis.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
A 6.9 μm Pixel-Pitch 3D Stacked Global Shutter CMOS Image Sensor with 3M Cu-Cu connections.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
A 6.9-µm Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC.
IEEE J. Solid State Circuits, 2018

A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2012
An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2006
High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2002
A 44-mm<sup>2</sup> four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller.
IEEE J. Solid State Circuits, 2002

2001
Wordline voltage generating system for low-power low-voltage flash memories.
IEEE J. Solid State Circuits, 2001

2000
Design of a sense circuit for low-voltage flash memories.
IEEE J. Solid State Circuits, 2000

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme.
IEEE J. Solid State Circuits, 2000


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