Tadayoshi Horita

According to our database, Tadayoshi Horita authored at least 24 papers between 1995 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement.

Itsuo Takanami, Tadayoshi Horita, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno

Trans. Comput. Sci., 2016

2015

An FPGA-Based Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Perceptron (Full Version).

Tadayoshi Horita, Itsuo Takanami, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno

Trans. Comput. Sci., 2015

2014

Multilayer Perceptrons Which Are Tolerant to Multiple Faults and Learnings to Realize Them.

Tadayoshi Horita, Itsuo Takanami, Kazuhiro Nishimura

Trans. Comput. Sci., 2014

A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings.

Tadayoshi Horita, Itsuo Takanami, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno

Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

2013

An FPGA-based multiple-weight-and-neuron-fault tolerant digital multilayer perceptron.

Tadayoshi Horita, Itsuo Takanami

Neurocomputing, 2013

2012

A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement.

Itsuo Takanami, Tadayoshi Horita

Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012

2011

An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications.

Tadayoshi Horita, Itsuo Takanami

Trans. Comput. Sci., 2011

2010

An FPGA-based fast classifier with high generalization property.

Tadayoshi Horita, Itsuo Takanami

SIGARCH Comput. Archit. News, 2010

2009

Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.

Kazuhiro Nishimura, Tadayoshi Horita, Masato Otsu, Itsuo Takanami

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

An Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation.

Tadayoshi Horita, Itsuo Takanami

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

A Computer Cluster for Tests of Parallel Programming Environments Including Operating Systems.

Tadayoshi Horita, Koichi Kitano, Koji Teramoto

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

2008

Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.

Tadayoshi Horita, Itsuo Takanami, Masatoshi Mori

IEICE Trans. Inf. Syst., 2008

An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches.

Tadayoshi Horita, Yuuji Katou, Itsuo Takanami

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2006

A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network.

Tadayoshi Horita, Takurou Murata, Itsuo Takanami

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2001

Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types.

Tadayoshi Horita, Itsuo Takanami

Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

2000

Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions.

Tadayoshi Horita, Itsuo Takanami

IEEE Trans. Computers, 2000

A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays.

Tadayoshi Horita, Itsuo Takanami

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

A System for Efficiently Self-Reconstructing E-1½-Track Switch Torus Arrays.

Tadayoshi Horita, Itsuo Takanami

Proceedings of the 5th International Symposium on Parallel Architectures, 2000

1999

Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions.

Tadayoshi Horita, Itsuo Takanami

Proceedings of the 1999 International Symposium on Parallel Architectures, 1999

1997

A built-in self-reconfigurable scheme for 3D mesh arrays.

Itsuo Takanami, Tadayoshi Horita

Proceedings of the 1997 International Symposium on Parallel Architectures, 1997

A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults.

Tadayoshi Horita, Itsuo Takanami

Proceedings of the 1997 International Symposium on Parallel Architectures, 1997

Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits.

Itsuo Takanami, Tadayoshi Horita

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996

Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults.

Tadayoshi Horita, Itsuo Takanami

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

Reconfigurable architectures for mesh-arrays with PE and link faults.

Itsuo Takanami, Tadayoshi Horita

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995