Tadato Yamagata

According to our database1, Tadato Yamagata authored at least 8 papers between 1990 and 1999.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
0
1
2
3
1
1
2
1
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1999
A 5.3-GB/s embedded SDRAM core with slight-boost scheme.
IEEE J. Solid State Circuits, 1999

1997
High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's.
IEEE J. Solid State Circuits, 1997

1996
A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond.
IEEE J. Solid State Circuits, 1996

SOI-DRAM circuit technologies for low power high speed multigiga scale memories.
IEEE J. Solid State Circuits, 1996

1995
Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs.
IEEE J. Solid State Circuits, November, 1995

1993
A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's.
IEEE J. Solid State Circuits, November, 1993

1992
A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure.
IEEE J. Solid State Circuits, December, 1992

1990
Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM.
IEEE J. Solid State Circuits, April, 1990


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