Tadato Yamagata
According to our database1,
Tadato Yamagata
authored at least 8 papers
between 1990 and 1999.
Collaborative distances:
Collaborative distances:
Timeline
1990
1991
1992
1993
1994
1995
1996
1997
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1999
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Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
1999
IEEE J. Solid State Circuits, 1999
1997
High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's.
IEEE J. Solid State Circuits, 1997
1996
A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond.
IEEE J. Solid State Circuits, 1996
IEEE J. Solid State Circuits, 1996
1995
IEEE J. Solid State Circuits, November, 1995
1993
A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's.
IEEE J. Solid State Circuits, November, 1993
1992
A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure.
IEEE J. Solid State Circuits, December, 1992
1990
Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM.
IEEE J. Solid State Circuits, April, 1990