Tadashi Tachibana

According to our database, Tadashi Tachibana authored at least 4 papers between 1988 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1999

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.

Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura

IEEE J. Solid State Circuits, 1999

1998

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register.

Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana

IEEE J. Solid State Circuits, 1998

1996

A 29-ns 64-Mb DRAM with hierarchical array architecture.

Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato

IEEE J. Solid State Circuits, 1996

1988

A 20-ns 256 K*4 FIFO memory.

Masashi Hashimoto, Masayoshi Nomura, Kenji Sasaki, Katsuo Komatsuzaki, Hiroyuki Fujiwara, Takashi Honzawa, Keiichiro Abe, Tadashi Tachibana, Norihisa Kitagawa

IEEE J. Solid State Circuits, April, 1988