Tadashi Sumi

According to our database1, Tadashi Sumi authored at least 8 papers between 1993 and 1997.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

1993
1994
1995
1996
1997
0
1
2
3
4
5
2
4
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1997
A multilevel QAM demodulator VLSI with wideband carrier recovery and dual equalizing mode.
IEEE J. Solid State Circuits, 1997

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply].
IEEE J. Solid State Circuits, 1997

1996
A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication.
IEEE J. Solid State Circuits, 1996

Leading-zero anticipatory logic for high-speed floating point addition.
IEEE J. Solid State Circuits, 1996

A 1.9-GHz single chip IF transceiver for digital cordless phones.
IEEE J. Solid State Circuits, 1996

A 286 MHz 64-b floating point multiplier with enhanced CG operation.
IEEE J. Solid State Circuits, 1996

1995
A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search.
IEEE J. Solid State Circuits, December, 1995

1993
A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture.
IEEE J. Solid State Circuits, December, 1993


  Loading...