Tadashi Nishimura

According to our database, Tadashi Nishimura authored at least 4 papers between 1988 and 1994.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1994

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology.

Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutarni Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara

IEEE J. Solid State Circuits, November, 1994

An experimental 256-Mb DRAM with boosted sense-ground scheme.

Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara

IEEE J. Solid State Circuits, November, 1994

1991

A 21-mW 4-Mb CMOS SRAM for battery operation.

Shuji Murakami, Kore-aki Fujita, Motomu Ukita, Kazuhito Tsutsumi, Yasuo Inoue, Osamu Sakamoto, Motoi Ashida, Yasumasa Nishimura, Yoshio Kohno, Tadashi Nishimura, Kenji Anami

IEEE J. Solid State Circuits, November, 1991

1988

An SOI structure for flash A/D converter.

Toshio Kumamoto, Masao Nakaya, Shigeru Kusunoki, Tadashi Nishimura, Nobuharu Yazawa, Yoichi Akasaka, Yasutaka Horiba

IEEE J. Solid State Circuits, February, 1988