Tadaaki Yamauchi
According to our database1,
Tadaaki Yamauchi
authored at least 19 papers
between 1996 and 2019.
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Bibliography
2019
A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Proceedings of the Embedded Flash Memory for Embedded Systems: Technology, 2018
2016
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C.
IEEE J. Solid State Circuits, 2016
7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
A 20uA/MHz at 200MHz microcontroller with low power memory access scheme for small sensing nodes.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
2015
Proceedings of the Symposium on VLSI Circuits, 2015
Technology/circuits joint evening panel discussion semiconductor industry in 2020: Evolution or revolution?
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the VLSI Design, Automation and Test, 2015
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C.
IEEE J. Solid State Circuits, 2014
2013
40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2001
IEEE J. Solid State Circuits, 2001
2000
IEEE J. Solid State Circuits, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1997
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997
1996
A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory.
IEEE J. Solid State Circuits, 1996