Tad A. Kwasniewski

According to our database, Tad A. Kwasniewski authored at least 64 papers between 1991 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

On-die power grid broadband model determination using a priori narrowband measurements.

Leonard MacEachem, Xin-Jie Wang, Tad A. Kwasniewski

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016

A reduced reference spur multiplying delay-locked loop.

Xinjie Wang, Tadeusz Kwasniewski

Int. J. Circuit Theory Appl., 2016

2015

Low noise CMOS voltage-control oscillator design methodology with emphasis on non-linear effect contributions, 2.4 GHz CMOS design example.

Zhe Jiang, Haizheng Guo, Tadeusz Kwasniewski

Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015

A DLL fractional M/N frequency synthesizer.

Haizheng Guo, Tadeusz Kwasniewski

Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015

A DLL-based period synthesis.

Haizheng Guo, Tadeusz Kwasniewski

Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015

2013

Spur analysis and reduction of edge combining DLL-based frequency multiplier.

Haizheng Guo, Xinjie Wang, Tadeusz Kwasniewski

Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

2012

A novel fractional-N PLL architecture with hybrid of DCO and VCO.

Chao He, Tadeusz Kwasniewski

Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

Bang-Bang CDR's acquisition, locking, and jitter tolerance.

Chao He, Tadeusz Kwasniewski

Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

A DLL-based fractional-N frequency synthesizer with a programmable injection clock.

Haizheng Guo, Tad A. Kwasniewski

Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

2011

A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system.

Harry Tai, Peter Noel, Tad A. Kwasniewski

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2010

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination.

Huong Ho, Valek Szwarc, Tad A. Kwasniewski

J. Signal Process. Syst., 2010

Optimized LNA for analog RF front-end circuit in brain-machine interface.

Haizheng Guo, Bo Wang, Bangli Liang, Tad A. Kwasniewski, Robert Sobot

Proceedings of the IEEE International Conference on Wireless Communications, 2010

2009

A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application.

Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski

IEEE Trans. Very Large Scale Integr. Syst., 2009

FIR filter optimization using bit-edge equalization in high-speed backplane data transmission.

Lei Zhang, Tadeusz Kwasniewski

Microelectron. J., 2009

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications.

Huong Ho, Valek Szwarc, Tad A. Kwasniewski

Int. J. Reconfigurable Comput., 2009

Modeling, Simulation and Analysis of High-Speed Serial Link Transceiver over Band-Limited Channel.

Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tadeusz Kwasniewski

Proceedings of the UKSim'11, 2009

A Simulator for High-Speed Backplane Transceivers.

Dianyong Chen, Bo Wang, Bangli Liang, Tadeusz Kwasniewski

Proceedings of the UKSim'11, 2009

A monolithic high modulation efficiency CMOS laser diode / modulator driver.

Bangli Liang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski, Zhigong Wang

Proceedings of the 2009 International Conference on Telecommunications, 2009

A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel.

Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tad A. Kwasniewski

Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

A full-rate truly monolithic CMOS CDR for low-cost applications.

Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski

Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously.

Dianyong Chen, Bo Wang, Bangli Liang, Tad A. Kwasniewski

Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

2008

A multi-mode sphere detector architecture for WLAN applications.

Ramin Shariat-Yazdi, Tad A. Kwasniewski

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Low complexity sphere decoding algorithms.

Ramin Shariat-Yazdi, Tad A. Kwasniewski

Proceedings of the 2008 5th International Symposium on Wireless Communication Systems, 2008

A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops.

Miao Li, Tad A. Kwasniewski, Shoujun Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 42-Gb/s Decision Circuit in 0.13µm CMOS.

Bangli Liang, Tad A. Kwasniewski, Dianyong Chen

Proceedings of the Sixth Annual Conference on Communication Networks and Services Research (CNSR 2008), 2008

Phase Noise Simulation and Modeling of ADPLL by SystemVerilog.

Tingjun Wen, Tadeusz Kwasniewski

Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008

2007

Design Considerations for a Direct RF Sampling Mixer.

Dianyong Chen, Wei Wang, Tadeusz Kwasniewski

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology.

Muhammad Usama, Tad A. Kwasniewski

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Dual Mode K-Best MIMO Detector Architecture and VLSI Implementation.

Ramin Shariat-Yazdi, Tadeusz Kwasniewski

Proceedings of the 14th IEEE International Conference on Electronics, 2007

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS.

Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction.

Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski

IEEE Trans. Circuits Syst. II Express Briefs, 2006

A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System.

Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

An eye detection technique for clock and data recovery applications.

Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 0.18µm CMOS clock and data recovery circuit with extended operation range.

Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations.

William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel

Proceedings of the 43rd Design Automation Conference, 2006

An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur.

Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider.

Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski

Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

A 0.18µm CMOS Receiver with Decision-feedback Equalization for Backplane Applications.

Miao Li, Tad A. Kwasniewski, Shoujun Wang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

PLL-Based Fractional-N Frequency Synthesizers.

Farhad Zarkeshvari, Peter Noel, Tad A. Kwasniewski

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications.

Miao Li, Peter Noel, Tad A. Kwasniewski, Shoujun Wang

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Turbo Codes - Digital IC Design.

Moeed Israr, Tad A. Kwasniewski

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

A Review of Common Receive-End Adaptive Equalization Schemes and Algorithms for a High-Speed Serial Backplane.

Charles E. Berndt, Tad A. Kwasniewski

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

A 0.18µm CMOS transceiver design for high-speed backplane data communications.

Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Decision feedback equalization for high-speed backplane data communications.

Jing Chen, Miao Li, Tad A. Kwasniewski

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An all-digital data recovery circuit optimization using Matlab/Simulink.

S. I. Ahmed, Tad A. Kwasniewski

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO.

Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski

Proceedings of the Third IASTED International Conference on Circuits, 2005

Design considerations for 2nd-order and 3rd-order bang-bang CDR loops.

Shoujun Wang, Haitao Mei, Mashkoor Baig, William Bereza, Tadeusz Kwasniewski, Rakesh H. Patel

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A signal integrity-based link performance simulation platform.

Yuming Tao, William Bereza, Rakesh H. Patel, Sergey Y. Shumarayev, Tad A. Kwasniewski

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Behavioral test benches for digital clock and data recovery circuits using Verilog-A.

S. I. Ahmed, Kent Orthner, Tadeusz Kwasniewski

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology.

Miao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Design and comparison of CMOS Current Mode Logic latches.

Muhammad Usama, Tad A. Kwasniewski

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2.4 GHz RF down-conversion mixers in standard CMOS technology.

Arif A. Siddiqi, Tad A. Kwasniewski

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer.

Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2001

A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator.

Lizhong Sun, Tadeusz Kwasniewski

IEEE J. Solid State Circuits, 2001

1999

Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis.

Lizhong Sun, Thierry Lepley, Franck Nozahic, Amaud Bellissant, Tad A. Kwasniewski, Bany Heim

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops.

Lizhong Sun, Tad A. Kwasniewski, Kris Iniewski

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A 1.25 GHz 0.35 μm monolithic CMOS PLL clock generator for data communications.

Lizhong Sun, Tad A. Kwasniewski

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1997

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications.

Manop Thamsirianunt, Tadeusz Kwasniewski

IEEE J. Solid State Circuits, 1997

1996

Is High Frequency Analog DFT Possible?

Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jérôme Wojcik

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1995

CMOS high-speed dual-modulus frequency divider for RF frequency synthesis.

Navid Foroudi, Tadeusz Kwasniewski

IEEE J. Solid State Circuits, February, 1995

1994

A chip set for pipeline and parallel pipeline FFT architectures.

Valek Szwarc, Luc Desormeaux, Wilson Wong, Clifford P. S. Yeung, Chong H. Chan, Tad A. Kwasniewski

J. VLSI Signal Process., 1994

A low power, single chip realization of a low-speed, low-delay CELP coder/decoder for indoor wireless systems.

D. P. Noel, Tad A. Kwasniewski, Samy A. Mahmoud, Wilf P. LeBlanc

Proceedings of 44th IEEE Vehicular Technology Conference: Creating Tomorrow's Mobile Systems, 1994

1993

Delta-sigma modulation in fractional-N frequency synthesis.

Tom A. D. Riley, Miles A. Copeland, Tad A. Kwasniewski

IEEE J. Solid State Circuits, May, 1993

1991

Baseband Trellis-Coded Modulation with Combined Equalization/Decoding for High Bit Rate Digital Subscriber Loops.

P. Mohanraj, David D. Falconer, Tad A. Kwasniewski

IEEE J. Sel. Areas Commun., 1991