Taavi Viilukas

According to our database, Taavi Viilukas authored at least 6 papers between 2006 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints.

Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara

J. Electron. Test., 2012

2011

Automated test bench generation for high-level synthesis flow ABELITE.

Taavi Viilukas, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Samary Baranov

Proceedings of the 9th East-West Design & Test Symposium, 2011

Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits.

Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara

Proceedings of the 16th European Test Symposium, 2011

2010

Constraint-based test pattern generation at the Register-Transfer Level.

Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2008

Mixed hierarchical-functional fault models for targeting sequential cores.

Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin

J. Syst. Archit., 2008

2006

High-Level Decision Diagram based Fault Models for Targeting FSMs.

Jaan Raik, Raimund Ubar, Taavi Viilukas

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006