Ta-Wei Liu

Orcid: 0009-0004-7519-437X

According to our database1, Ta-Wei Liu authored at least 12 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Petroller: Altering the Virtual Reality Controller with an Attachable Prop-based Haptic for Embodied Virtual Companion.
Proceedings of the SIGGRAPH Asia 2024 XR, SA 2024, Tokyo, Japan, December 3-6, 2024, 2024

2023
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.
IEEE J. Solid State Circuits, March, 2023

2022
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips.
IEEE J. Solid State Circuits, 2022

2021
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips.
IEEE J. Solid State Circuits, 2021

A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2017
Energy-aware run-time task partition and allocation in dynamic partial reconfigurable systems.
J. Syst. Archit., 2017


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